The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
One common application for programmable devices is to serve as a prototype for application specific integrated circuits (ASICs). Programmable devices can implement the logic of an ASIC design, thereby acting as a functional equivalent to the ASIC. The programmable device can then be tested to ensure the ASIC design functions as intended. Programmable devices allow prototypes of ASICs to be created and evaluated quickly and inexpensively, especially as compared to the cost of custom fabrication of an ASIC.
ASIC designs often include gated clocks signals to dynamically shut down portions of the ASIC that are not in use, thereby conserving power. A gated clock is a clock signal that is a function of one or more base clock signal and/or one or more other inputs, such as clock enable signals. A base clock is a pin, register, or clock output port of a functional block such as a phase-locked loop (PLL) that provides a clock signal for synchronizing registers and other components of a programmable device. Typically, a gate clock signal is created by passing at least one base clock signal through combinatorial logic gates and/or registers.
A typical large ASIC design might include hundreds of different clock trees. However, some programmable devices have only a limited amount of resources available for global clock networks. Thus, the large number of clock trees of the ASIC design can overwhelm the resources of the programmable device.
Additionally, even if a programmable device has sufficient resources to implement all of the numerous clock trees of a complex ASIC design, timing closure problems often arise. Programmable logic cells are relatively slow as compared with dedicated logic circuits. Programamble devices typically implement gated clock logic of an ASIC design using programmable logic cells. Because of their relatively slow operating speed, the programmable logic cells implementing gated clock logic introduce substantial clock skew between registers and other components using the base clock signal and those using gated clock signals.
To overcome this problem, designers can replace gated clock networks of the ASIC design with functionally equivalent input logic when adapting this type of ASIC design for implementation on a programmable device. The functionally equivalent input logic typically allows a register to be clocked directly from a base clock signal, rather than a gated clock signal. The functionally equivalent input logic modifies the data input to a register so that the functionality of the register in response to clock enable signal is unchanged. Previously, designers would have to perform this conversion manually, which is not only tedious and time-consuming but also potentially error-prone.
It is therefore desirable for a system and method to automatically identify gated clock signals in a design and to automatically convert these gated clock signals to functionally equivalent input logic. It is further desirable for the system and method to ensure that the input logic substituted for gated clock signals in a programmable device does not inadvertently introduces glitches or other errors.